This standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 package body along with this clause 1 documentation. The information annex A is a guide to users and is not part of this standard, but suggests ways in which one might use this package
IEEE 1164-1993
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IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)